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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
- Utilizes industry standard 8M X 16 DDR Synchronous DRAMs in TSOP package , industry standard EEPROM(SPD) in TSSOP package - 200pin SO-DIMM - Vdd=Vddq=2.5v 0.2V
DESCRIPTION
The MH8D64AKQC is 8388608 - word x 64-bit Double Data Rate(DDR) Sy nchronous DRAM mounted module. This consists of 4 industry standard 8M x 16 DDR Sy nchronous DRAMs in TSOP with SSTL_2 interf ace which achiev es v ery high speed data rate up to 133MHz. This socket-ty pe memory m odule is suitable f or main memory in computer systems and easy to interchange or add modules.
- Double data rate architecture; two data transf ers per clock cy c le - Bidirectional, data strobe (DQS) is transmitted/receiv ed with data - Dif f erential clock inputs (CLK and /CLK)
- DLL aligns DQ and DQS transitions with CLK transition edges of DQS
FEATURES
Max. Frequency CLK Access Time [component level]
Type name
MH8D64AKQC-75 MH8D64AKQC-10
133MHz 100MHz
+ 0.75ns + 0.8ns
- Commands entered on each positiv e CLK edge - Data and data mask ref erenced to both edges of DQS - 4bank operation concontrolled by BA0,BA1(Bank Address ,discrete) - /CAS latency - 2.0/2.5 (programmable) - Burst length- 2/4/8 (programmable) - Burst Ty pe - sequential/interleav e(programmable) - Auto precharge / All bank precharge controlled by A10 - 4096 ref resh cy c les /64ms - Auto ref resh and Self ref resh - Row address A0-11 / Column address A0-8 - SSTL_2 Interf ace - Module 1bank Conf igration
APPLICATION
Main memory unit for Note PC, Mobile etc.
PCB Outline
(Front) (Back)
1 2
199 200
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN CONFIGURATION
PIN NO. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 PIN NAME Vref Vss DQ0 DQ1 Vdd DQS0 DQ2 Vss DQ3 DQ8 Vdd DQ9 DQS1 Vss DQ10 DQ11 Vdd CK0 /CK0 Vss DQ16 DQ17 Vdd DQS2 DQ18 Vss DQ19 DQ24 Vdd DQ25 DQS3 Vss DQ26 DQ27 Vdd NC NC Vss NC NC Vdd NC PIN NO. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 PIN NAME Vref Vss DQ4 DQ5 Vdd DM0 DQ6 Vss DQ7 DQ12 Vdd DQ13 DM1 Vss DQ14 DQ15 Vdd Vdd Vss Vss DQ20 DQ21 Vdd DM2 DQ22 Vss DQ23 DQ28 Vdd DQ29 DM3 Vss DQ30 DQ31 Vdd NC NC Vss NC NC Vdd NC PIN NO. 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 PIN NAME NC Vss CK2 /CK2 Vdd CKE1 NC A12 A9 Vss A7 A5 A3 A1 Vdd A10/AP BA0 /WE /S0 NC Vss DQ32 DQ33 Vdd DQS4 DQ34 Vss DQ35 DQ40 Vdd DQ41 DQS5 Vss DQ42 DQ43 Vdd Vdd Vss Vss DQ48 DQ49 Vdd PIN NO. 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 PIN NAME NC Vss Vss Vdd Vdd CKE0 NC A11 A8 Vss A6 A4 A2 A0 Vdd BA1 /RAS /CAS /S1 NC Vss DQ36 DQ37 Vdd DM4 DQ38 Vss DQ39 DQ44 Vdd DQ45 DM5 Vss DQ46 DQ47 Vdd /CK1 CK1 Vss DQ52 DQ53 Vdd NC: No Connect PIN NO. 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 PIN NAME DQS6 DQ50 Vss DQ51 DQ56 Vdd DQ57 DQS7 Vss DQ58 DQ59 Vdd SDA SCL VddSPD VddID PIN NO. 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 PIN NAME DM6 DQ54 Vss DQ55 DQ60 Vdd DQ61 DM7 Vss DQ62 DQ63 Vdd SA0 SA1 SA2 NC
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Block Diagram
/S0
DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
22
LDQS LDM
/S
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D0 2 3 4 5 6 7 8 9 10 11 12 13 14 15
/S
UDQS UDM
DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
LDQS LDM
/S
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D2 2 3 4 5 6 7
/S
UDQS UDM
8 9 10 11 12 13 14 15
/S
LDQS LDM
LDQS LDM
UDQS UDM
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
0 1 D3 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SERIAL PD
UDQS UDM
CKE0 /RAS /CAS /WE BA0,BA1,A<11:0> VddSPD Vref Vdd Vss VddID
D0 - D3 D0 D0 D0 D0 D3 D3 D3 D3
CK0 /CK0 CK1 /CK1 CK2 /CK2
2loads SCL SA0 SA1 2loads SA2
A0 A1 A2
SDA WP
0loads
NOTE: DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. Vdd ID strap connections: (for memory device Vdd, VddQ) Strap out (open): Vdd=VddQ Strap in (closed): Vdd=VddQ
SPD D0 - D3 D0 - D3 D0 - D3
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
PIN FUNCTION
SYMBOL TYPE DESCRIPTION
Clock: CK0-2 and /CK0-2 are dif f erential clock inputs. All address and control input signals are sampled on the crossing of the positiv e edge of CK0-2 and negativ e edge of /CK0-2. Output (read) data is ref erenced to the crossings of CK0-2 and /CK0-2 (both directions of c rossing). Clock Enable: CKE0-1 controls internal clock. When CKE0-1 is low, internal clock f or the f ollowing cy c le is ceased. CKE0-1 is also used to select auto / self ref resh. After self ref resh mode is started, CKE0-1 becomes asy nchronous input. Self ref resh is maintained as long as CKE0-1 is low. Chip Select: When /S0-1 is high, any command means No Operation.
CK0-2,/CK0-2
Input
CKE0
Input
/S0 /RAS, /CAS, /WE
Input Input
Combination of /RAS, /CAS, /WE defines basic commands.
A0-11 specif y the Row / Column Address in conjunction with BA0,1. The Row Address is specif ied by A0-11. The Column Address is specif ied by A0-8. A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is perf ormed. When A10 is high at a precharge command, all banks are precharged. Bank Address: BA0-1 specif y one of f our banks in SDRAM to which a command is applied. BA0-1 must be set with ACT, PRE, READ, WRITE commands.
A0-11
Input
BA0-1 DQ 0-64 DQS0-7
Input
Input / Output Data Input/Output: Data bus Input / Output
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM0-7 is sampled HIGH along with that input data during a WRITE access. DM0-7 are sampled on both edges of DQS0-7. Although DM pins are input only, the DM0-7 loading matches the DQ0-63 and DQS0-7 loading.
DM0-7 Vdd, Vss Vddspd Vref SDA SCL SA0-2 VddID
Input
Power Supply Power Supply for the memory array and peripheral circuitry. Power Supply Input Power Supply for SPD SSTL_2 reference voltage.
This is a bidirectional pin used to transf er data into or out of the SPD EEPROM. This signal is used to clock data into and out of the SPD EEPROM. A resistor
Input / Output A resistor must be connected to Vdd to act as a pullup.
Input / Output may be connected f rom the SCL to Vdd to act as a pullup. Input Output
Address pins used to select the Serial Presence Detect. Vdd identif ication f lag
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BASIC FUNCTIONS
The MH8D64AKQC provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table.
/CK0 CK0 /S0 /RAS /CAS /WE CKE0 A10
Chip Select : L=select, H=deselect Command Command Command Ref resh Option @ref resh command Precharge Option @precharge or read/write command def ine basic commands
Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (auto-precharge,READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-precharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE0 =H] REFA command starts auto-refresh cycle. Refresh address including bank address are generated internally. After this command, the banks are precharged automatically.
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
COM M AND TRUTH TABLE
COMMAND Deselect No Operation Row Address Entry & Bank Activate Single Bank Precharge Precharge All Banks Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Column Address Entry & Read Column Address Entry & Read with Auto-Precharge Auto-Refresh Self-Refresh Entry Self-Refresh Exit Burst Terminate Mode Register Set MNEMONIC DESEL NOP ACT PRE PREA WRIT E CKE n-1 H H H H H H CKE n X X H H H H /S H L L L L L /RAS X H L L L H /CAS X H H H H L /WE X H H L L L BA0,1 X X V V X V A10 /AP X X V L H L A0-9, note 11 X X V X X V
WRITEA
H
H
L
H
L
L
V
H
V
READ
H
H
L
H
L
H
V
L
V
READA REFA REFS REFSX TERM MRS
H H H L L H H
H H L H H H H
L L L H L L L
H L L X H H L
L L L X H H L
H H H X H L L
V X X X X X L
H X X X X X L
V X X X X X V 1 2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should not be used) for read bursts with autoprecharge enabled, and for write bursts. 2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to be written to the selected Mode Register.
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE
Current State IDLE /S H L L L L L L L ROW ACTIVE H L L L L L L L L READ (AutoPrecharge Disabled) H L L L /RAS /CAS /WE X H H H L L L L X H H H H L L L L X H H H X H H L H H L L X H H L L H H L L X H H L X H L X H L H L X H L H L H L H L X H L H X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 Address Command DESEL NOP TERM NOP NOP ILLEGAL 2 2 Action Notes
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TERM READ / READA WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM Bank Active, Latch RA NOP Auto-Refresh Mode Register Set NOP NOP NOP Begin Read, Latch CA, Determine Auto-Precharge Begin Write, Latch CA, Determine Auto-Precharge Bank Active / ILLEGAL Precharge / Precharge All ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) Terminate Burst Terminate Burst, Latch CA, READ / READA Begin New Read, Determine Auto-Precharge WRITE WRITEA ACT PRE / PREA REFA MRS
4 5 5
2
3
L L L L L
H L L L L
L H H L L
L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
ILLEGAL Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL 2
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State WRIT E (AutoPrecharge Disabled) /S H L L L /RAS /CAS /WE X H H H X H H L X H L H X X BA BA, CA, A10 Address Command DESEL NOP TERM Action NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL Terminate Burst, Latch CA, READ / READA Begin Read, Determine AutoPrecharge WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM Terminate Burst, Latch CA, Begin Write, Determine AutoPrecharge Bank Active / ILLEGAL Terminate Burst, Precharge ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL 3 3 Notes
L L L L L READ with AUTO PRECHARGE H L L L L L L L L WRITE with AUTO PRECHARGE H L L L L L L L L
H L L L L X H H H H L L L L X H H H H L L L L
L H H L L X H H L L H H L L X H H L L H H L L
L H L H L X H L H L H L H L X H L H L H L H L
BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add
2
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS DESEL NOP TERM ILLEGAL Bank Active / ILLEGAL PRECHARGE/ILLEGAL ILLEGAL ILLEGAL NOP (Continue Burst to END) NOP (Continue Burst to END) ILLEGAL 2 2
READ / READA ILLEGAL WRITE / WRITEA ACT PRE / PREA REFA MRS ILLEGAL Bank Active / ILLEGAL PRECHARGE/ILLEGAL ILLEGAL ILLEGAL 2 2
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State PRE CHARGING /S H L L L L L L L ROW ACTIVATING H L L L L L L L WRITE RECOVERING H L L L L L L L /RAS /CAS /WE X H H H L L L L X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TERM Action NOP (Idle after tRP) NOP (Idle after tRP) ILLEGAL 2 2 2 4 Notes
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TERM ILLEGAL NOP (Idle after tRP) ILLEGAL ILLEGAL NOP (Row Active after tRCD) NOP (Row Active after tRCD) ILLEGAL
2 2 2 2
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TERM ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP NOP ILLEGAL
2 2 2 2
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE (continued)
Current State REFRESHING /S H L L L L L L L MODE REGISTER SETTING H L L L L L L L /RAS /CAS /WE X H H H L L L L X H H H L L L L X H H L H H L L X H H L H H L L X H L X H L H L X H L X H L H L X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add X X BA BA, CA, A10 BA, RA BA, A10 X Op-Code, Mode-Add Address Command DESEL NOP TERM Action NOP (Idle after tRC) NOP (Idle after tRC) ILLEGAL Notes
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS DESEL NOP TERM ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP (Idle after tRSC) NOP (Idle after tRSC) ILLEGAL
READ / WRITE ILLEGAL ACT PRE / PREA REFA MRS ILLEGAL ILLEGAL ILLEGAL ILLEGAL
ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No Operation NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed.
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
FUNCTION TRUTH TABLE for CKE
Current State SELFREFRESH CKE0 CKE0 /S0 /RAS /CAS /WE n n-1 H L L L L L L POWER DOWN H L L ALL BANKS IDLE H H H H H H H L ANY STATE other than listed above H H L L ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CK0 and other inputs asynchronously . A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. X H H H H H L X H L H L L L L L L X H L H L X H L L L L X X X X X L H L L L L X X X X X X X H H H L X X X X X L X H H H L X X X X X X X H H L X X X X X X L X H H L X X X X X X X X H L X X X X X X X H X H L X X X X X X X Add X X X X X X X X X X X X X X X X X X X X X X INVALID Exit Self-Refresh (Idle after tRC) Exit Self-Refresh (Idle after tRC) ILLEGAL ILLEGAL ILLEGAL NOP (Maintain Self-Refresh) INVALID Exit Power Down to Idle NOP (Maintain Self-Refresh) Refer to Function Truth Table Enter Self-Refresh Enter Power Down Enter Power Down ILLEGAL ILLEGAL ILLEGAL Refer to Current State =Power Down Refer to Function Truth Table Begin CLK Suspend at Next Cycle Exit CLK Suspend at Next Cycle Maintain CLK Suspend 3 3 2 2 2 2 2 2 2 2 Action Notes 1 1 1 1 1 1 1
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
SIMPLIFIED STATE DIAGRAM
POWER APPLIED
POWER ON
PREA
PRE CHARGE ALL
REFS
SELF REFRESH
MRS
REFSX REFA
MODE REGISTER SET
MRS
IDLE
AUTO REFRESH
CKEL CKEH
Active Power Down
CKEH
ACT
POWER DOWN
CKEL
ROW ACTIVE
WRITE WRITE WRITEA READA READ READ READ
BURST STOP
WRIT E
READ
TERM
WRITEA READA
READA
WRITEA
PRE
PRE PRE
READA
PRE CHARGE Automatic Sequence Command Sequence
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or multifunctioning. 1. Apply VDD before or the same time as VDDQ 2. Apply VDDQ before or at the same time as VTT & Vref 3. Maintain stable condition for 200us after stable power and CLK, apply NOP or DSEL 4. Issue precharge command for all banks of the device 5. Issue EMRS 6. Issue MRS for the Mode Register and to reset the DLL 7. Issue 2 or more Auto Refresh commands 8. Maintain stable condition for 200 cycle After these sequence, the SDRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when all banks in discrete are in idle state. After tMRD from a MRS command, the DDR DIMM is ready for new command. BA1 BA0 A11 A10 A9 0 0 0 0 0 A8 DR A7 0 A6 A5 A4 A3 BT A2 A1 A0 BL CK0 /CK0 /S0 /RAS /CAS /WE BA0 LTMODE BA1 A11-A0 BL CL 000 001 010 011 100 101 110 111 NO YES /CAS Latency R R 2 R R R 2.5 R Burst Length 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 BT= 0 R 2 4 8 R R R R
V
BT= 1 R 2 4 8 R R R R
Latency Mode
Burst Type
Sequential Interleaved
DLL Reset
0 1
R: Reserved for Future Use
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
EXTENDED MODE REGISTER
DLL disable / enable mode can be programmed by setting the extended mode register (EMRS). The extended mode register stores these data until the next EMRS command, which may be issued when all banks in discrete are in idle state. After tRSC from a EMRS command, the DDR DIMM is ready for new command.
CK0 /CK0 /S0 /RAS /CAS /WE
BA1 BA0 A11 A10 A9 0 1 0 0 0
A8 0
A7 0
A6 0
A5 0
A4 0
A3 0
A2
A1
A0
BA0 BA1 A11-A0
V
QFC DS DD
DLL Disable
0 1
DLL enable DLL disable
Drive Strength
0 1
Normal Weak
QFC
0 1
Disable Enable
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Preliminary Spec.
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MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
/CLK CLK Command Address DQS DQ CL= 2 BL= 4
Read Y
Write Y
Q0 Q1 Q2 Q3
D0 D1 D2 D3
/CAS Latency
Burst Length
Burst Length
Initial Address
BL Sequential 0 1 2 3 8 4 5 6 7 0 1 4 2 3 0 2 1 1 2 3 4 5 6 7 0 1 2 3 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 3 4 5 6 7 0 1 2 3 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4
Column Addressing Interleaved 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 0 1 2 3 0 1 1 0 3 2 5 4 7 6 1 0 3 2 1 0 2 3 0 1 6 7 4 5 2 3 0 1 3 2 1 0 7 6 5 4 3 2 1 0 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
A2 0 0 0 0 1 1 1 1 -
A1 0 0 1 1 0 0 1 1 0 0 1 1 -
A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
ABSOLUTE M AXIMUM RATINGS
Symbol Vdd VI VO IO Pd Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta = 25C Conditions with respect to Vss with respect to Vss with respect to Vss Ratings -0.5 ~ 3.7 -0.5 ~ Vdd+0.5 -0.5 ~ Vdd+0.5 50 4 0 ~ 70 -45 ~ 100 Unit V V V mA W C C
DC OPERATING CONDITIONS
(Ta=0 ~ 70C
Symbol Vdd Vref VIH(DC) VIL(DC) VIN(DC)
, unless otherwise noted)
Limits Parameter Supply Voltage Input Reference Voltage High-Level Input Voltage Low-Level Input Voltage Input Voltage Level, CK0 and /CK0 Min. 2.3 0.49*Vdd Vref + 0.18 -0.3 -0.3 0.36 Vref - 0.04 Typ. 2.5 0.5*Vdd Max. 2.7 0.51*Vdd Vdd+0.3 Vref - 0.18 Vdd + 0.3 Vdd + 0.6 Vref + 0.04 Unit Notes V V V V V V V 7 6 5
VID(DC) Input Differential Voltage, CK0 and /CK0 VTT I/O Termination Voltage
CAPACITANCE
(Ta=0 ~ 70C Symbol CI(A) CI(C) CI(K) CI/O , Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted) Parameter Input Capacitance, address pin Input Capacitance, control pin Input Capacitance, CK0 pin Input Capacitance, I/O pin Test Condition
VI - 1.25V f =100MHz VI = 25mVrm
Limits(max.) 35 35 30 15
Unit Notes pF pF pF pF 11 11 11 11
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 16
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70C
Sy m bol
, Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
Parameter/Test Conditions Limits(max) -75 -10 Unit Notes
IDD0
OPERATING CURRENT: One Bank(Discrete); Activ e-Precharge; t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing twice per clock cy c le; address and control inputs changing once per clock cy c le OPERATING CURRENT: One Bank(Discrete); Activ e-Read-Precharge; Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0 mA;Address and control inputs changing once per clock cy c le PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; power-down mode; CKE VIL (MAX); t CK = t CK MIN IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle; CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs changing once per clock cy c le ACTIVE POWER-DOWN STANDBY CURRENT: One bank activ e; power-down mode; CKE VIL (MAX); t CK = t CK MIN ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN); One bank; Activ e-Precharge; t RC = t RAS MAX; t CK = t CK MIN; DQ,DM and DQS inputs changing twice per clock cy c le; address and other control inputs changing once per clock cy c le OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One bank activ e(Discrete); Address and control inputs changing once per clock cy c le; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
480
460
mA
IDD1
540
520
mA
IDD2P
80
80
mA
IDD2N
160
160
mA
IDD3P
160
160
mA
IDD3N
300
280
mA
IDD4R
840
800
mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank activ e(Discrete); Address and control inputs changing once per IDD4W clock cy c le; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs changing twice per clock cy c le IDD5 IDD6 AUTO REFRESH CURRENT: t RC = t RFC (MIN) SELF REFRESH CURRENT: CKE 0.2V
840
800
mA
760 12
720 12
mA mA
9
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70C Symbol , Vdd = VddQ = 2.5 0.2V, Vss =VssQ= 0V, unless otherwise noted) Parameter/Test Conditions Limits Min. Vref + 0.35 Vref - 0.35 0.7 0.5*Vdd-0.2 -5 -8 Vdd + 0.6 0.5*Vdd+0.2 5 8 Max. Unit Notes V V V V A A 7 8
VIH(AC) High-Level Input Voltage (AC) VIL(AC) Low-Level Input Voltage (AC) VID(AC) Input Differential Voltage, CLK and /CLK VIX(AC) Input Crossing Point Voltage, CLK and /CLK IOZ Ii Off-state Output Current /Q floating Vo=0~VDDQ Input Current / VIN=0 ~ VddQ
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 17
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS (Component Level)
(Ta=0 ~ 70C , Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted)
AC Characteristics Sy m bol tAC Parameter DQ Output Valid data delay time f rom CLK//CLK Min. -0.75 -0.75 0.45 0.45 CL=2.5 tCK tDS tDH tDIPW tHZ tLZ tDQSQ CLK cy c le time CL=2 Input Setup time (DQ,DM) Input Hold time(DQ,DM) DQ and DM input pulse width (f or each input) Data-out-high impedance time f rom CLK//CLK Data-out-low impedance time f rom CLK//CLK DQ Valid data delay time f rom DQS tCLmin or tCHmin tHP0.75 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 0.9 0.9 0.4 0.9 0.6 1.1 0.6 1.25 10 0.5 0.5 1.75 -0.75 -0.75 +0.75 +0.75 +0.5 tCLmin or tCHmin tHP-1.0 0.75 0.35 0.35 0.2 0.2 15 0 0.4 0.25 1.1 1.1 0.4 0.9 0.6 1.1 0.6 1.25 15 10 0.6 0.6 2 -0.8 -0.8 +0.8 +0.8 +0.6 15 ns ns ns ns ns ns ns 14 14 7.5 -75 Max. +0.75 +0.75 0.55 0.55 15 Min. -0.8 -0.8 0.45 0.45 8 -10 Max. +0.8 +0.8 0.55 0.55 15 Unit ns ns tCK tCK ns Notes
tDQSCK DQ Output Valid data delay time f rom CLK//CLK tCH tCL CLK High lev el width CLK Low lev el width
tHP
Clock half period
ns
tQH tDQSS tDQSH tDQSL tDSS tDSH tMRD
Output DQS v alid window Write command to f irst DQS latching transition DQS input High lev el width DQS input Low lev el width DQS f alling edge to CLK setup time DQS f alling edge hold time f rom CLK Mode Register Set command cy c le time
ns tCK tCK tCK tCK tCK ns ns tCK tCK ns ns tCK tCK 16 15
tWPRES Write preamble setup time tWPST tWPRE tIS tIH tRPST tRPRE Write postamble Write preamble Input Setup time (address and control) Input Hold time (address and control) Read postamble Read preamble
19 19
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 18
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
AC TIMING REQUIREMENTS(Continues)
(Ta=0 ~ 70C , Vdd = VddQ = 2.5 0.2V, Vss = VssQ = 0V, unless otherwise noted) AC Characteristics Symbol tRAS tRC tRFC tRCD tRP tRRD tWR tDAL tWT R tXSNR tXSRD tXPNR tXPRD tREFI Row Active time Row Cycle time(operation) Auto Ref. to Active/Auto Ref. command period Row to Column Delay Row Precharge time Act to Act Delay time Write Recovery time Auto Precharge write recovery + precharge time Internal Write to Read Command Delay Exit Self Ref. to non-Read command Exit Self Ref. to -Read command Exit Power down to command Exit Power down to -Read command Average Periodic Refresh interval Parameter Min. 45 65 75 20 20 15 15 35 1 75 200 1 1 15.6 -75 Max. 120,000 Min. 50 70 80 20 20 15 15 35 1 80 200 1 1 15.6 -10 Max. 120,000 Unit Notes ns ns ns ns ns ns ns ns tCK ns tCK tCK tCK us 18 17
Output Load Condition
(f or component measurement)
DQS
DQ
VREF
VTT =V REF 50ohm VO U Zo=50 ohm 30pF VREF
VREF
Output Timing Measurement Reference Point
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 19
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Notes
1. All voltages referenced to Vss. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK//CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and VIH(AC). 4. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level. 5. VREF is expected to be equal to 0.5*VddQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed +/-2% of the DC value. 6. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 7. VID is the magnitude of the difference between the input level on CLK and the input level on /CLK. 8. The value of VIX is expected to equal 0.5*VddQ of the transmitting device and must track variations in the DC level of the same. 9. Enables on-chip refresh and address counters. 10. IDD specification are tested after the device is properly initialized. 11. This parameter is sampled. VddQ = +2.5V+/-0.2V, Vdd = +2.5V+/-0.2V, f =100MHz, Ta = 25 C , VOUT(DC)= VddQ/2, VOUT(PEAK TO PEAK) = 25mV, DM inputs are grouped with I/O pins - reflecting the fact that they are matched in laoding (to faciliate trace matching at the board level). 12. The CLK//CLK input reference level (for timing referenced to CLK//CLK) is the point at which CLK and /CLK cross; the input reference level for signals other than CLK//CLK, is VREF. 13. Inputs are not recognized as valid until VREF stabilized. Exception: during the period before VREF stabilizes, CKE=< 0.3VddQ is recognized as LOW. 14. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ), or begins driving (LZ). 15. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 16. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CLK edge. A valid transition is defined as monotonic, and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from High-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 17. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 18. tXPRD should be 200 tCLK in the condition of the unstable CLK operation during the power down mode. 19. For command/address and CLK & /CLK slew rate >1.0V/ns.
O
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 20
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
(Component Level) Read Operation /CLK CLK Cmd & Add.
tDQSCK tRPRE tIS tIH VREF tCK tCH tCL
Valid Data tRPST
DQS
tQH tAC tDQSQ
DQ
Write Operation / tDQSS=max. /CLK CLK DQS
tDQSS tWPRES tWPRE tDSS tWPST
tDQSL tDS
tDQSH tDH
DQ
Write Operation / tDQSS=min. /CLK CLK DQS
tDQSS tWPRES tWPRE tDQSL tDS tDQSH tDH tDSH tWPST
DQ
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 21
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
OPERATIONAL DESCRIPTION (Component Level)
BANK ACTIVATE The DDR SDRAM has four independent banks. Each bank is activated by the ACT command with the bank addresses (BA0,1). A row is indicated by the row address A11-0. The minimum activation interval between one bank and the other bank is tRRD. M aximum 2 ACT commands are allowed within tRC,although the number of banks which are active concurrently is not limited. PRECHARGE The PRE command deactivates the bank indicated by BA0,1. When multiple banks are active, the precharge all command (PREA,PRE+A10=H) is available to deactivate them at the same time. After tRP from the precharge, an ACT command to the same bank can be issued. Bank Activation and Precharge All (BL=8, CL=2)
/CLK CLK
2 ACT command / tRCmin tRCmin PRE tRAS Xb tRCD Y BL/2 0 1 Xb tRP Xb ACT
Command
ACT tRRD
ACT READ
A0-9,11
Xa
A10
Xa
Xb
BA0,1
00
01
00
01
DQS
DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Precharge all
A precharge command can be issued at BL/2 from a read command without data loss.
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 22
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
READ After tRCD from the bank activation, a READ command can be issued. 1st Output data is available after the /CAS Latency from the READ, followed by (BL-1) consecutive data when the Burst Length is BL. The start address is specified by A11,A8-A0, and the address sequence of burst data is defined by the Burst Type. A READ command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous output data by interleaving the multiple banks. When A10 is high at a READ command, the auto-precharge(READA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at BL/2 after READA. The next ACT command can be issued after (BL/2+tRP) from the previous READA.
Multi Bank Interleaving READ (BL=8, CL=2)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Qa Qa Qa Qa Qa Qa Qa Qa Qb Qb Qb Qb Qb Qb Qb Qb
ACT tRCD Xa Xa
READ ACT Y 0 Xb Xb
READ PRE Y 0 0
00
00
10
10
00
Burst Length /CAS latency
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 23
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
READ with Auto-Precharge (BL=8, CL=2)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Qa Qa Qa Qa Qa Qa Qa Qa
BL/2 + tRP ACT tRCD Xa Xa 00 Y 1 00 READ BL/2 tRP Xb Xb 00 ACT
Internal precharge start
READ Auto-Precharge Timing (BL=8)
/CLK CLK Command
ACT READ BL/2
CL=2.5 DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
CL=2
DQ
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Qa
Internal Precharge Start Timing
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 24
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
WRITE After tRCD from the bank activation, a WRITE command can be issued. 1st input data is set from the WRITE command with data strobe input, following (BL-1) data are written into RAM , when the Burst Length is BL. The start address is specified by A11,A8-A0, and the address sequence of burst data is defined by the Burst Type. A WRITE command may be applied to any active bank, so the row precharge time (tRP) can be hidden behind continuous input data by interleaving the multiple banks. From the last data to the PRE command, the write recovery time (tWRP) is required. When A10 is high at a WRITE command, the auto-precharge(WRITEA) is performed. Any command(READ,WRITE,PRE,ACT) to the same bank is inhibited till the internal precharge is complete. The next ACT command can be issued after tDAL from the last input data cycle. Multi Bank Interleaving WRITE (BL=8)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7 Db0 Db1 Db2 Db3 Db4 Db5 Db6 Db7
ACT Xa Xa Xa 00
WRITE ACT tRCD Ya 0 00 Xb Xb 10 tRCD
WRITE Yb 0 10
PRE
PRE
0 00
0
10
WRITE with Auto-Precharge (BL=8)
/CLK CLK Command A0-9,11 A10 BA0,1 DQS DQ
Da0 Da1 Da2 Da3 Da4 Da5 Da6 Da7
ACT Xa Xa 00
WRITE tRCD Y 1 tDAL
ACT Xb Xb 00
00
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 25
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
BURST INTERRUPTION [Read Interrupted by Read] Burst read operation can be interrupted by new read of any bank. Random column access is allowed. READ to READ interval is minimum 1CLK. Read Interrupted by Read (BL=8, CL=2)
/CLK CLK Command A0-9,11 A10 BA0,1
READ READ Yi 0 00 Yj 0 00 READ Yk 0 10 READ Yl 0 01
DQS DQ
Qai0 Qai1 Qaj0 Qaj1 Qaj2 Qaj3 Q a k Q a k Q a k Q a k Q a k Q a k Qal0 Qal1 Qal2 Qal3 Qal4 Qal5 Qal6 Qal7
[Read Interrupted by precharge] Burst read operation can be interrupted by precharge of the same bank. READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. As a result, READ to PRE interval determines valid data length to be output. The figure below shows examples of BL=8.
/CLK CLK Command DQS DQ Command
READ PRE
Q0 Q1 Q2 Q3 Q4 Q5
Read Interrupted by Precharge (BL=8)
READ
PRE
CL=2.5
DQS DQ Command DQS DQ
Q0 Q1 Q0 Q1 Q2 Q3
READ PRE
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 26
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Read Interrupted by Precharge (BL=8)
/CLK CLK Command DQS DQ Command
READ
Q0 Q1 Q2 Q3 Q4 Q5
READ
PRE
PRE
CL=2.0
DQS DQ Command DQS DQ
Q0 Q1 Q0 Q1 Q2 Q3
READ PRE
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 27
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Burst Stop] Burst read operation can be interrupted by a burst stop command(TERM ). READ to TERM interval is minimum 1 CLK. A TERM command to output disable latency is equivalent to the /CAS Latency. As a result, READ to TERM interval determines valid data length to be output. The figure below shows examples of BL=8.
Read Interrupted by TERM (BL=8)
/CLK CLK Command DQS DQ Command
READ
TERM
Q0 Q1 Q2 Q3 Q4 Q5
READ
TERM
CL=2.5
DQS DQ Command DQS DQ Command DQS DQ Command
READ
Q0 Q1 Q2 Q3 Q4 Q5 Q0 Q1 Q0 Q1 Q2 Q3
READ TERM
READ
TERM
TERM
CL=2.0
DQS DQ Command DQS DQ
Q0 Q1 Q0 Q1 Q2 Q3
READ TERM
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 28
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Read Interrupted by Write with TERM]
Read Interrupted by TERM (BL=8)
/CLK CLK Command
READ
TERM
WRITE
CL=2.5
DQS DQ Command
READ
TERM
Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5
WRITE
CL=2.0
DQS DQ
Q0 Q1 Q2 Q3 D0 D1 D2 D3 D4 D5 D6 D7
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 29
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Write] Burst write operation can be interrupted by write of any bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write Interrupted by Write (BL=8)
/CLK CLK Command A0-9,11 A10 BA0,1
WRITE WRITE Yi 0 00 Yj 0 00 WRITE Yk 0 10 WRITE Yl 0 00
DQS DQ
Dai0 Dai1 Daj0 Daj1 Daj2 Daj3 D a k 0 D a k 1 D a k 2 D a k 3 D a k 4 D a k 5 Dal0 Dal1 Dal2 Dal3 Dal4 Dal5 Dal6 Dal7
[Write interrupted by Read] Burst write operation can be interrupted by read of the same or the other bank. Random column access is allowed. Internal WRITE to READ command interval(tWTR) is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "don't care". tWTR is referenced from the first positive edge after the last data input.
/CLK CLK Command A0-9,11 A10 BA0,1 DM tWT R QS DQ
Dai0 Dai1 Qaj0 Qaj1 Qaj2 Qaj3 Qaj4 Qaj5 Qaj6 Qaj7
Write Interrupted by Read (BL=8, CL=2.5)
WRITE Yi 0 00
READ Yj 0 00
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 30
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Write interrupted by Precharge] Burst write operation can be interrupted by precharge of the same or all bank. Random column access is allowed. tWR is referenced from the first positive CLK edge after the last data input.
Write Interrupted by Precharge (BL=8, CL=2.5)
/CLK CLK Command A0-9,11 A10 BA0,1 DM QS DQ
Dai0 Dai1
WRITE Yi 0 00
PRE
00
tWR
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MITSUBISHI ELECTRIC
17.May.2001 31
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Initialize and Mode Register sets]
/CLK CLK
Command A0-9,11 A10 BA0,1 DQS DQ
NOP
PRE
EMRS
MRS
PRE
AR
AR
MRS
ACT
Code
Code
Xa
1
Code
Code
1
Code
Xa
10
00
00
Xa
tMRD
Extended Mode Register Set
tMRD
tRP
tRFC
tRFC
tMRD
Mode Register Set, Reset DLL
[AUTO REFRESH] Single cycle of auto-refresh is initiated with a REFA(/CS=/RAS=/CAS=L,/WE=CKE=H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 128M bits memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an auto refresh, all banks must be in the idle state. Auto-refresh to auto-refresh interval is minimum tRFC . Any command must not be supplied to the device before tRFC from the REFA command. Auto-Refresh
/CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1
tRFC NOP or DESELECT
Auto Refresh on All Banks
MIT-DS-0419-0.1
Auto Refresh on All Banks MITSUBISHI ELECTRIC
17.May.2001 32
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[S ELF REFRESH] Self -refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,/WE=H,CKE=L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Self-Refresh
/CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1
X X tXSNR Self Refresh Exit Act tXSRD
Y Y
Read
MIT-DS-0419-0.1
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Asynchronous S ELF REFRESH] Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command (/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE for longer than tXSNR/tXSRD.
Asynchronous Self-Refresh
/CLK CLK /CS /RAS /CAS /WE CKE A0-11 BA0,1
max 2 tCLK
tXSNR Self Refresh Exit Act
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
[Power DOWN] The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT required in the condition of the stable CLK operation during the power down mode. Power Down by CKE
/CLK CLK CKE Command
PRE NOP
Standby Power Down
NOP Valid
CKE Command
ACT NOP
Active Power Down
NOP Valid
tXPNR/ tXPRD
[DM CONTROL] DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to write mask latency is 0. DM Function(BL=8,CL=2)
/CLK CLK Command
Write READ
DM DQS DQ
D0 D1 D3 D4 D5 D6 D7
Don't Care
Q0
Q1
Q2
Q3
Q4
Q5
Q6
masked by DM=H
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 35
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table I
Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Function described Number of Serial PD Bytes Written during Production Total # bytes of SPD memory device Fundamental memory type # Row Addresses on this assembly # Column Addresses on this assembly # Module Banks on this assembly Data Width of this assembly... ... Data Width continuation Voltage interface standard of this assembly
SDRAM Cycletime at Max. Supported CAS Latency (CL). -75 -10 -75 -10
SPD enrty data 128 256 Bytes SDRAM DDR 12 9 1BANK x64 0 SSTL2.5V 7.5ns 8.0ns +0.75ns +0.8 ns
None-parity,Non-ECC
SPD DATA(hex) 80 08 07 0C 09 01 40 00 04 75 80 75 80 00 80 10 00 01 0E 04 0C 01 02 20 00 A0 A0 75 80 00 00 00 00 50 3C 50 2D 32
Cycle time for CL=2.5 SDRAM Access from Clock tAC for CL=2.5 DIMM Configuration type (Non-parity,Parity,ECC) Refresh Rate/Type SDRAM width,Primary DRAM Error Checking SDRAM data width
MIimum Clock Delay, Random Column Access
15.625uS/SR x16 N/A 1 clock 2, 4, 8 4bank 2.0, 2.5 0 1
Differential Clock VDD + 0.2V -75 -10 -75 -10 -75
Burst Lengths Supported Number of Device Banks CAS# Latency CS# Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes:General SDRAM Cycle time(2nd highest CAS latency) Cycle time for CL=2
SDRAM Access form Clock(2nd highest CAS latency)
10ns 10ns +0.75ns +0.8ns Undefined Undefined Undefined Undefined 20ns 15ns 20ns
24
tAC for CL=2
25
SDRAM Cycle time(3rd highest CAS latency)
-10
26
-75 SDRAM Access form Clock(3rd highest CAS latency) -10
27 28 29 30
Minimum Row Precharge Time (tRP) Minimum Row Active to Row Active Delay (tRRD) RAS to CAS Delay Minv (tRCD)
-75
45ns 50ns
Active to Precharge Min (tRAS)
-10
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 36
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Serial Presence Detect Table II
31 32 Density of each bank on module
-75
64MByte
0.9nS 1.1nS 0.9nS 1.1nS 0.5nS 0.6nS 0.5nS 0.6nS -10 -75 -10 -75
10 90 B0 90 B0 50 60 50 60 00 00 93 19 1CFFFFFFFFFFFFFF
Command and Address signal input setup time Command and Address signal input hold time
33
34 35 36-61 62
Data signal input setup time Data signal input hold time Superset Information (may be used in future) SPD Revision
-10 -75 -10
option 0 Check sum for -75
63
Checksum for bytes 0-62 Check sum for -10
64-71
Manufactures Jedec ID code per JEP-108E
MITSUBISHI
72
Manufacturing location
Manufacturing Location
XX
73-90
Manufactures Part Number
MH8D64AKQC-75 MH8D64AKQC-10
4D4838443634414B51432D37352020202020 4D4838443634414B51432D31302020202020
91-92 93-94 95-98 99-127 128-255
Revision Code Manufacturing date Assembly Serial Number Reserved Open for Customer Use
PCB revision year/week code serial number Undefined Undefined
rrrr yyww ssssssss 00 00
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
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Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
EEPROM Components A.C. and D.C. Characteristics
Symbol VCC VSS VIH VIL VOL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Output Low Voltage Min. 2.2 0 Vccx0.7 -1 Limits Typ. 0 Max. 5.5 0 Vcc+0.5 Vccx0.3 0.4 Units V V V V V
EEPROM A.C.Timing Parameters (Ta=0 to 70C )
Symbol fSCL TI TAA TBUF THD:STA TLOW THIGH TSU:STA THD:DAT TSU:DAT TR TF TSU:STO TDH TWR Parameter SCL Clock Frequency Noise Supression Time Constant at SCL, SDA inputs SCL Low to SDA Data Out Valid
Time the Bus Must Be Free before a New Transmission Can Start
Limits Min. Max. 100 200 3.5 4.7 4.0 4.7 4.0 4.7 0 250 1 300 4.0 100 10
Units KHz ns us us us us us us us ns us ns us ns ms
Start Condition Hold Time Clock Low Time Clock High Time Start Condition Setup Time Data In Hold Time Data In Setup Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Condition Setup Time Data Out Hold Time Write Cycle Time
tWR is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle.
TF TLOW
THIGH
TR
SCL
TSU:STO TSU:STA THD:STA THD:DAT TSU:DAT
SDA IN
TAA TDH TBUF
SDA OUT
MIT-DS-0419-0.1
MITSUBISHI ELECTRIC
17.May.2001 38
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
OUTLINE
31.75 20.00 4.00 6.00
4.00
0.25Max 2.55 MIT-DS-0419-0.1 Unit.mm 17.May.2001 39
MITSUBISHI ELECTRIC
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1.These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. 2.Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor hom e page (http://www.mitsubishichips.com). 4.When using any or all of the information contained in these materials, including product data, diagrams, charts, programs and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5.Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
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